1. Field of the Invention
The present invention relates to an alignment structure of a main amplifier in a memory device in which main amplifiers are aligned between different memory cell arrays to thereby reduce power consumption of the main amplifiers.
2. Description of the Prior Art
A conventional memory device includes, with reference to FIG. 1, a control and address buffer unit 10 for outputting row and column address signals RADS and CADS, row decoder enable signal REN, and first to fourth main amplifier enable signals MEN0-MEN3 when row and column address strobe signals/RAS and/CAS, a write enable signal /WE, an output enable signal /OE and an address signal ADS are provided from an external source; first and second row decoders 20 and 30 for respectively outputting word line select signals WL0-WLn according to the row decoder enable signal REN and the row address signal RADS; a column decoder 40 for outputting bit line select signals BL0-BLm in accordance with the column decoder enable signal CEN and the column address signal CADS provided from the control and address buffer 10; first and second memory cell arrays 50 and 60 for outputting stored data in accordance with both the bit line select signals BL0-BLm provided from the column decoder 40 and the word line select signals WL0-WLn respectively provided from the first and second row decoders 20 and 30; first and second sense amplifiers 51 and 61 for amplifying the data provided from the first and second memory cell arrays 50 and 60; first and second column switches 52 and 62 for switching an output of the data CD0-CD3 and/CD0-/CD3 amplified by the first and second sense amplifiers 51 and 61; first to fourth main amplifiers 71-74 for respectively amplifying the data CD0-CD3 and /CD0-/CD3 provided through the first and second column switches 52 and 62; and an input/output buffer 80 for buffering the data amplified by the main amplifiers 71-74 and outputting the bufferred data Dout to an outside of the memory device.
The first and second memory cell arrays 50 and 60 respectively includes a plurality of cells. The memory device is exemplarily constructed as having four main amplifiers.
The operation of the conventional memory device as constructed above will now be described with reference to FIG. 1.
First, when the memory device is operated to be read, the output enable signal /OE becomes active. Subsequently, as the row address strobe signal /RAS and the column address strobe signal /CAS become respectively active, the row address RADS and the column address CADS are respectively latched by the control and address buffer unit 10. Accordingly, the first and second row decoder 20 and 30 are respectively enabled in accordance with the row decoder enable signal REN provided from the control and address buffer 10 for decoding the row address RADS latched by the control and address buffer 10, and output the word line select signals WO0-WLn to the first and second memory cell arrays 50 and 60. In the meantime, the column decoder 40 is enabled by the column decoder enable signal CEN for decoding the column address CADS latched by the control and address buffer 10, and outputs the bit line select signals BL0-BLm to the first and second memory cell arrays 50 and 60.
Accordingly, the first and second memory cell arrays 50 and 60 respectively output the data stored at a cell designated in accordance with the word line select signals WL0-WLn and the bit line select signals BL0-BLm to the first and second sense amplifiers 51 and 61. The first and second sense amplifiers 51 and 61 amplify the inputted data and output the amplified data to the first and second column switches 52 and 62. The first and second column switches are turned on or turned off in response to the bit line select signals BL0-BLm, and provide the data 52, 62, CD0-CD3 and /CD0-/CD3 to the first to fourth main amplifiers 71-74.
At this time, among the first to fourth main amplifiers 71-74, one main amplifier is enabled by the main amplifier enable signals MEM0-MEN3, so that the inputted data is amplified and the amplified data is outputted to the input/output buffer 80 through an input/output data line CDS and /CDS. Subsequently, the input/output buffer 80 buffers the inputted data, and the bufferred data Dout is outputted to an outside of the memory device.
In the meantime, when the memory device is operated to be written, the write enable signal /WE becomes active, and a data Din is inputted from an external source to the input/output buffer 80. After that, a process that inputted data is stored at the first and second memory cell arrays 50 and 60 is the opposite to the read operation, thus, description of the corresponding operation is omitted here.
However, such a conventional memory device as described above has disadvantages in that when the bit line selected by the column decoder is changed, time for the data to be transmitted to each main amplifier is varied according to a length of the data line corresponding to the changed bit line. Therefore, the main amplifier is unnecessarily in an enabled state for a long time, causing increasing power consumption.